1. Field of the Invention
The invention relates to active matrix displays, for instance of the liquid crystal type using low temperature polycrystalline silicon thin film transistors as active elements within the matrix.
2. Description of the Related Art
A known type of active matrix display has active circuitry within a matrix of addressing lines in order to control the optical properties of a display material, such as liquid crystal. FIG. 1 of the accompanying drawings illustrates the structure of a typical active matrix display. A regular rectangular array of active matrix elements, such as 1, is arranged as rows addressed by a scan driver 2 and columns addressed by a data driver 3. The circuit of a typical picture element or pixel is illustrated at 4.
Each pixel comprises a display element (not shown) which is effectively in parallel with a hold capacitor 5. The hold capacitor 5 is connected between the source of a thin film field effect transistor 6 and a common supply line or to the previous gate line. The gate of the transistor 6 is connected to a scan electrode 8 which is common to all of the pixels of the row and which is connected to a respective output of the scan driver 2. The drain of the transistor 6 is connected to a data electrode 7 which is common to all of the pixels of the column and which is connected to a respective output of the data driver 3.
In use, rows of pixel display data are supplied by the data driver 3 to the data electrodes 7 in synchronism with scan pulses which are supplied by the scan driver 2 to the scan electrodes 8 in a cyclically repeating sequence. Thus, the rows of pixels are refreshed one at a time until all of the rows have been refreshed so as to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
When the scan electrode 8 of each pixel receives a scan pulse from the scan driver 2, the voltage on the data electrode 7 causes the hold capacitor 5 to be charged. When the scan pulse is removed, the transistor 6 isolates the hold capacitor 5 from the data electrode 7 so that the optical property of the associated display element corresponds to the voltage across the hold capacitor 5 until it is refreshed during the next frame.
In active matrix liquid crystal displays, the voltage stored on the hold capacitor 5 is used to modulate the optical properties of a thin layer of liquid crystal. In a known type of display, the transistors 6 forming switching elements are embodied as amorphous silicon thin film transistors. Between refresh cycles of each pixel, the dynamic behaviour of the voltage stored in the capacitor 5 is of considerable importance in determining the picture quality.
Most liquid crystal devices have a non-linear and time dependent relationship between the applied voltage and the surface charge present on the liquid crystal. This effect, known as dielectric anisotropy, implies that the effective capacitance of the liquid crystal device is a function of the applied voltage and the response time of the liquid crystal. In a conventional active matrix liquid crystal device pixel, the non-ideal liquid crystal capacitance Clc, shown at 9 in FIG. 2, is in parallel with a fixed storage capacitor Cs. When the pixel is addressed by supplying a scan pulse to the scan electrode 8, the gate voltage of the transistor 6 goes high for a relatively short time so as to allow the display to be refreshed sufficiently rapidly to avoid visible flicker. The charging time for the capacitance comprising the parallel combination of the capacitor 5 and the display element 9 is therefore sufficiently short for the voltage dependence of the liquid crystal capacitance Clc to have no substantial effect so that the capacitance Clc may be considered constant for the duration of the scan pulse.
However, during the interval between scan pulses, the transistor 6 substantially isolates the capacitor 5 and the display element 9 so that the charge across the parallel combination remains substantially constant. As the liquid crystal responds to the applied voltage, the capacitance Clc changes so that the final voltage across the display element is not equal to the amplitude of the charging pulse and does not therefore correspond to the data voltage which was supplied to the data electrode 7 during scanning of the pixel. In the case of a liquid crystal having positive dielectric anisotropy, the capacitance increases so that the voltage across the liquid crystal display element falls.
The effects of dielectric anisotropy are illustrated in FIGS. 3a to 3c of the accompanying drawings, each of which shows superimposed graphs of gate voltage and display transmission against time. FIG. 3a illustrates the liquid crystal response to a single scan pulse per refresh cycle. The voltage on the data line provides the gate voltage in the form of a relatively short pulse. The desired transmission value is indicated on the left hand vertical axis but the actual transmission characteristic of the liquid crystal display element is such that a lower than expected transmission is provided. In other words, as the liquid crystal responds to the voltage, the capacitance increases and the voltage across the liquid crystal decreases so that the transmission does not reach the desired value.
FIG. 3b corresponds to FIG. 3a but illustrates the effect of several refresh cycles of the pixel with the same data signal. In particular, three refresh cycles are shown. Thus, it is possible to achieve the desired transmission by applying a sequence of scan pulses to the pixel.
FIG. 3c, which corresponds to FIGS. 3a and 3b, illustrates the effect of charging the liquid crystal capacitance from a lower impedance voltage source. This can be achieved, for example, by switching the transistor 6 on for a longer period of time so that the hold capacitor 5 and the liquid crystal capacitance Clc are charged from the respective output of the data driver 3 which has a relatively low output impedance. The liquid crystal display element therefore achieves the desired transmission value but the rate at which the display can be refreshed is greatly reduced so that undesirable visual artefacts, such as flicker, becomes visible.
A known technique for reducing the effects of non-ideal capacitance is to make the capacitance Cs of the hold capacitor much greater than the non-ideal liquid crystal capacitance Clc. This approach is acceptable for typical nematic materials which typically have a surface charge density of 10.sup.-4 C/m.sup.2. There are, however, liquid crystal modes which exhibit a much larger difference in surface charge density between switched states. To drive these materials using the conventional active matrix scheme would necessitate supplying this potentially large value of charge during the time that the scan line is high. Since there is not enough time for the liquid crystal material to respond during the scan time, this would require a very large storage capacitor, a very high data voltage and a conventionally sized capacitor, or a compromise between these methods. In general, it would be impractical to consider using the conventional active matrix scheme in such circumstances because the combinations of large capacitances and/or voltages would have a disadvantageous effect on the aperture ratio and power consumption of the display. Examples of such materials include liquid crystal devices with a spontaneous polarisation, such as surface stabilised ferroelectrics, or a field-induced spontaneous polarisation, such as electroclinics, helioelectrics, deformed helix ferroelectrics, antiferroelectrics, random phases, and columnars.
In addition to the effects of dielectric anisotropy, the effect of leakage current through the thin film transistor 6 may also give rise to undesirable visual artefacts. The leakage current is that current which flows across the transistor channel when the gate voltage is below the threshold voltage. Such a leakage current may cause the voltage stored in the hold capacitor 5 to decrease since the leakage current through the thin film transistor tends to allow the charges stored in the hold capacitor 5 tend to escape therefrom. Thus, if the leakage current is too high, then the voltage across the liquid crystal element decays significantly for the frame period. As a result, the transmission characteristics of the element will change significantly between refreshes so that the display produces visible flicker.
Recent advances in thin film transistor processing technology have resulted in the development of high performance polysilicon thin film transistors. In particular, it is now possible to fabricate such transistors at temperatures which are low enough to be compatible with the glass substrates used in displays. Further, such transistors can now be made with improved drive capability compared to conventional amorphous silicon thin film transistors and may therefore be used not only within each pixel of the display but also for high speed peripheral drive circuitry, such as in the drivers 2 and 3. The manufacturing cost of integrated displays may thus be reduced.
At the pixel level, polysilicon transistors may be made smaller than amorphous silicon transistors with the advantages that the aperture ratio can be improved and scan voltage feedthrough can be reduced. However, the leakage current of a polysilicon thin film transistor is much worse than that of an amorphous silicon thin film transistor. The off-state leakage represents one of the most variable parameters over a display panel and is highly dependent on the gate-source voltage and drain-source voltage of the transistors 6. These characteristics therefore represent a major problem in adopting polysilicon thin film transistors as switching elements in active matrix liquid crystal display panels.
FIG. 4 of the accompanying drawings shows graphs of drain current on a logarithmic scale against gate-source voltage for two different device temperatures and two different drain-source voltages. Decreasing the drain-source voltage provides an exponential reduction in the leakage current at all temperatures. Thus, as is known, it is possible to reduce leakage current by field reduction at the drain of the transistor. F. Okumura and K. Sera, A.M.L.C.D., p24-27 (1994) discloses several techniques for achieving this, such as Lightly Doped Drain (LDD) Structures, Offset Gate (OG) Structures, Active Gates (AG) and Multiple Gates.
LDD and OG structures reduce the field at the drain but also have a deleterious effect on the on-state current and hence the speed of such devices. This is not ideal for integrated displays because it requires different processes to be used for the pixel transistors, where off-current is crucial, and for the drivers, where high speeds are crucial. The use of extra processing steps is undesirable and may increase the cost of manufacture.
An alternative technique is the use of multiple gates which amounts to using two or more thin film transistors in series as illustrated in FIG. 5 of the accompanying drawings. The single gate transistor 6 of the arrangement shown in FIGS. 1 and 2 is replaced by a multiple gate transistor equivalent to the transistors 6a and 6b of FIG. 5. However, there may not be sufficient field reduction across the devices to prevent excess leakage current so that this technique has often been applied together with the LDD technique.
Another known technique shown in FIG. 6 of the accompanying drawings is to use an additional hold capacitor 10 at the junction of the multiple gate structure, which is effectively between the transistors 6a and 6b. However, it is doubtful whether such an arrangement will provide sufficient hold times to allow the use of polysilicon thin film transistors in displays without undesirable visual artefacts.
FIG. 7 of the accompanying drawings illustrates another technique for extending the hold time over several frames as disclosed in Japanese laid-open Patent Application No. 5-142573. This technique involves "boot-strapping" by connecting a unity voltage gain amplifier 11 with its input to the capacitor 5 and the display element 9 and its output to the junction between the transistors 6a and 6b. In other words, the circuit of FIG. 7 is provided with a feedback function through the unity voltage gain amplifier 11, so that the voltage across the capacitor 5 and the display element 9 appears at the junction of the series-connected thin film transistors 6a and 6b. If the buffer amplifier 11 were ideal and drew no charge from the capacitor 5 and the capacitance of the display element 9, leakage from the liquid crystal would be eliminated.
EP 0 586 155 discloses an active matrix liquid crystal display as shown in FIG. 8a of the same general type so that shown in FIG. 1. However, the active circuitry for each pixel differs in that there is provided a buffer amplifier 11 having unity voltage gain. The input of the amplifier 11 is connected to the source of the transistor 6 and to the hold capacitor 5 whereas the output of the amplifier 11 is connected to the liquid crystal display element 9. The amplifier 11 has a very high input impedance and a relatively low output impedance.
When the pixel is addressed by applying a scan pulse to the scan electrode 8, the transistor 6 is switched on so that the hold capacitor 5 charges to the voltage which is present on the data electrode 7. Between scan pulses on the electrode 8, the transistor 6 is switched off. The output of the amplifier 11 follows the voltage across the capacitor 5 and supplies this voltage to the display element 9.
The output impedance of the amplifier 11 is relatively low so that the display element 9 is effectively voltage driven. Accordingly, the voltage across the display element 9 remains substantially constant. The liquid crystal is therefore subjected to a voltage step which is applied for the entire frame refresh time.
Although EP 0 586 155 is concerned with overcoming the effect of current leakage between the electrodes of the display element 9 which would cause the voltage across the display element to fall between consecutive refreshes, the effect of liquid crystal dielectric anisotropy would also be substantially reduced or eliminated.
However, the technique disclosed in EP 0 586 155 may not sufficiently reduce the leakage current through the thin film transistor 6, resulting in an undesirable decrease in the voltage across the hold capacitor 5 which in turn leads to an decrease in the voltage across the display element 9.
Specifically, in the circuit of EP 0 586 155 as illustrated in FIG. 8a, the buffer amplifier 11 causes the voltage across the display element 9 to be set equal to the voltage across the hold capacitor 5, so that the voltage across the display element 9 remains unchanged irrespective of the dielectric anisotropy of the liquid crystal material. However, the charges stored in the hold capacitor 5 can "escape" therefrom through the transistor 6 due to the leakage current flowing through the transistor 6, resulting in the voltage across the hold capacitor being reduced. As a result, the voltage across the display element 9 is reduced.